1. Field of the Invention
This invention relates to the field of digital electronics, and more particularly to random access memory (RAM) data ports.
2. Description of the Related Art
In the prior art, data input/output (I/O) functions for memory cells in integrated circuits (ICs) have been confined to fixed-width word-length operations. For example, applications involving the use of an eight-bit data word utilize a memory cell having an eight-bit data port, and applications involving a sixteen-bit data word utilize a different memory cell with a hardwired sixteen-bit data port. This specificity of memory cells based on word length prevents the widespread application and re-use of general memory configurations.
In the construction of electronic circuits, many skilled practitioners use what are referred to as “standard cells” to build their circuits. These standard cells are predesigned circuit building blocks resident in a library of such building blocks. Because the standard cells are individually designed and tested before they are added to the library, performance characteristics for the standard cells are predictable. Using predesigned standard cells can reduce the amount of time between conception of a circuit design and production of a working circuit prototype.
Similarly, many designers use programmable gate arrays (PGAs) to implement digital circuit designs. Gate arrays are integrated circuits with standard logic cells (e.g., NAND gates, NOR gates, registers, etc.) already resident in an integrated circuit. Typically, gate array ICs include thousands of these individual cells with mechanisms for interconnecting the cells. The designer merely identifies the interconnection of the resident logic cells to implement his circuit design. The mechanism for interconnecting the cells may be a one-time fuse mechanism, or a programmable mechanism allowing for reuse of the gate array IC in another design.
For instance, using a field-programmable gate array (FPGA), such as one from the XILINX product line, an erasable programmable ROM chip (EPROM) or electrically erasable programmable ROM chip (EEPROM) may be used to store the programmable configuration information for one or more PGAs. To implement a new logic design on the same PGAs, the designer erases the EPROM and loads in a new set of configuration information. During the startup cycle, the PGAs adopt the new configuration by interconnecting the logic cells based on the new configuration information. Using computer aided design (CAD) tools to generate the configuration information, a recursive design process can cycle from one working design implementation to a revised working design implementation in as little time as a single day.
One drawback of gate arrays is that the number of logic cells of any particular type (e.g., NAND gate, eight-bit shift register, etc.) is fixed. For larger sized cells such as RAM (random access memory) cells, this limitation is of greater concern, because of the relatively fewer number of such cells. It is therefore beneficial to make these larger sized cells as generic as possible to increase their utility for different design needs.
With respect to RAM cells, different applications entail different RAM configurations, e.g., eight-bit word access, sixteen-bit word access, serial (one-bit) access, etc. For this reason, many gate arrays and standard cell libraries include cells of each type to serve all applications. Unfortunately, the unused configurations in a gate array constitute wasted IC area that could be utilized for other needed logic cells.
In the prior art, dual port RAM circuits have been used to increase the utility of the RAM. Examples of dual port RAM for use in video systems are U.S. Pat. Nos. 4,633,441; 4,799,053; and 5,195,056 to Ishimoto, Van Aken et al., and Pinkham et al., respectively. A dual port RAM circuit has two data ports for accessing the contents of the RAM.
In a dual port RAM, the ports may have the same or different data widths. For instance, a dual port RAM may have a first port providing eight-bit access and a second port providing one-bit or serial access to the same memory. This configuration is useful for applications requiring both byte access and serial access, such as for parallel-to-serial and serial-to-parallel conversion. However, other applications may require different configurations. For example, in a video application, a designer may require a first port providing thirty-two-bit access to write pixel data and a second port providing eight-bit access for reading out eight-bit segments of pixel RGB data. In the prior art, the eight-bit/one-bit dual port RAM cell cannot be used in the thirty-two-bit/eight-bit configuration needed in the video application.
Dual port RAM cells provide an improvement in the manner in which memory is accessed. However, designers are limited to the fixed-width configuration available in the hardwired circuit, or else an application specific circuit must be designed to provide the needed configuration. Further, it is inefficient in the standard cell and gate array environments to provide for dual port RAM cells of each possible dual port combination.